Wide-bandgap high- k Y2 O3 as passivating interlayer for enhancing the electrical properties and high-field reliability of n-Ge metal-oxide-semiconductor capacitors with high- k HfTiO gate dielectric

High- k and wide-bandgap Y2 O3 was proposed as an interlayer in n-Ge metal-oxide-semiconductor (MOS) capacitor with HfTiO gate dielectric for passivating its dielectric/Ge interface, and thus improving its electrical properties and high-field reliability. Results showed that as compared to the Ge MOS capacitor with HfTiO dielectric, the sample with HfTiO/ Y2 O3 dielectric had better electrical properties such as higher dielectric constant (k=24.4), lower interface-state density, and less frequency-dependent C-V dispersion, and also better reliability with less increases in gate leakage and interface states after high-field stressing. This should be attributed to the excellent interfacial quality of Y2 O3 /Ge with no appreciable growth of unstable GeOx at the interface as confirmed by transmission electron microscopy. Moreover, Y 2 O3 can also act as a barrier against the diffusions of Ge, Hf, and Ti, thus further improving the interface quality. © 2009 American Institute of Physics.published_or_final_versio

Effects of sputtering and annealing temperatures on MOS capacitor with HfTiON gate dielectric

In this work, Al/HfTiON/n-Si capacitors with different sputtering and annealing temperatures are studied. Larger accumulation capacitance and flat-band voltage are observed for samples with higher sputtering or post-deposition annealing temperature. Gate conduction mechanisms are only affected by sputtering temperature slightly. The flat-band voltage shift and interface-state density at midgap under high-field gate injection and substrate injection are investigated, and the results imply electron detrapping in the gate dielectric. ©2009 IEEE.published_or_final_versionThe IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC 2009), Xi'an, China, 25-27 December 2009. In Proceedings of EDSSC, 2009, p. 209-21

Effects of annealing gas species on the electrical properties and reliability of Ge MOS capacitors with high-k Y 2O 3 gate dielectric

In this work, Ge MOS capacitors with Y 2O 3 gate dielectric were fabricated. The effects of annealing in N 2, NH 3 O 2 or NO ambient were investigated. Experimental results demonstrated that the NO annealing could improve both electrical properties and reliability of Ge MOS devices with Y 2O 3 dielectric. On the other hand, the NH 3 annealing resulted in H-related traps while the O 2 annealing suffered from extra GeO x growth, thus both degrading the performance of the devices. ©2009 IEEE.published_or_final_versionThe IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC 2009), Xi'an, China, 25-27 December 2009. In Proceedings of EDSSC, 2009, p. 243-24

Suppressed growth of unstable low-fr GeOx interlayer in Ge metal-oxide-semiconductor capacitor with high-k gate dielectric by annealing in water vapor

The effects of water vapor added in the N2 annealing of high-k HfTiON gate dielectric on Ge metal-oxide-semiconductor capacitor are investigated. Both transmission-electron microscopy and ellipsometry indicate that, as compared to dry-N2 annealing, the wet-N2 annealing can greatly suppress the growth of unstable low-k GeOx at the dielectric/Ge interface, thus resulting in smaller equivalent dielectric thickness, as well as less interface states and dielectric charges. All these are attributed to the hydrolyzable property of GeOx in water. Moreover, the wet-N2 annealed capacitor has ten times lower gate-leakage current due to its better dielectric morphology as confirmed by atomic force microscopy. © 2007 American Institute of Physics.published_or_final_versio

Improved properties of Ge MOS capacitors with HfTiON or HfTiO gate dielectric by using wet-NO ge-surface pretreatment

HfTiO/GeOxNy and HfTiON/GeOxNy stack gate dielectrics are prepared by using wet-NO or wet-N2O pretreatment on Ge substrate. Experimental results show that the wet NO pretreatment can lead to excellent interface properties, gate leakage properties and device reliability, especially for the HfTiON/GeOxNy dielectric. The involved mechanisms lie in the roles of N in blocking oxygen diffusion and Ge out-diffusion and suitable N incorporation in the GeO xNy interlayer, which effectively suppress further growth of GeOxNy interlayer and the growth of unstable GeO x during subsequent processing. © 2008 IEEE.published_or_final_versio

Heterogeneous photodegradation of pentachlorophenol and iron cycling with goethite, hematite and oxalate under UVA illumination

2009-2010 > Academic research: refereed > Publication in refereed journalAccepted ManuscriptPublishe

Enhanced performance of Si MOS capacitors with HfTaOxNy gate dielectric by using AlOxNy or TaOxNy interlayer

Si MOS capacitors with HfTa oxide and oxynitride as gate dielectric were fabricated. Moreover, AlOxNy or TaOxN y was used as the interlayer between HfTa oxynitride and Si substrate to improve the electrical quality of the capacitors. Experimental results showed that the HfTaOxNy capacitor with TaO xNy interlayer achieved better performance with larger capacitance and smaller leakage current than its counterpart with AlO xNy interlayer. © 2008 IEEE.published_or_final_versio

PPI-IRO: A two-stage method for protein-protein interaction extraction based on interaction relation ontology

Mining Protein-Protein Interactions (PPIs) from the fast-growing biomedical literature resources has been proven as an effective approach for the identifi cation of biological regulatory networks. This paper presents a novel method based on the idea of Interaction Relation Ontology (IRO), which specifi es and organises words of various proteins interaction relationships. Our method is a two-stage PPI extraction method. At fi rst, IRO is applied in a binary classifi er to determine whether sentences contain a relation or not. Then, IRO is taken to guide PPI extraction by building sentence dependency parse tree. Comprehensive and quantitative evaluations and detailed analyses are used to demonstrate the signifi cant performance of IRO on relation sentences classifi cation and PPI extraction. Our PPI extraction method yielded a recall of around 80% and 90% and an F1 of around 54% and 66% on corpora of AIMed and Bioinfer, respectively, which are superior to most existing extraction methods. Copyright © 2014 Inderscience Enterprises Ltd

Improved electrical properties of Ge p-MOSFET with HfO 2 gate dielectric by using TaO xN y interlayer

The electrical characteristics of germanium p-metal-oxide-semiconductor (p-MOS) capacitor and p-MOS field-effect transistor (FET) with a stack gate dielectric of HfO 2TaO xN y are investigated. Experimental results show that MOS devices exhibit much lower gate leakage current than MOS devices with only HfO 2 as gate dielectric, good interface properties, good transistor characteristics, and about 1.7-fold hole-mobility enhancement as compared with conventional Si p-MOSFETs. These demonstrate that forming an ultrathin passivation layer of TaO xN y on germanium surface prior to deposition of high- k dielectrics can effectively suppress the growth of unstable GeO x, thus reducing interface states and increasing carrier mobility in the inversion channel of Ge-based transistors. © 2008 IEEE.published_or_final_versio

Impacts of Ti content and annealing temperature on electrical properties of Si MOS capacitors with HfTiON gate dielectric

Proceedings of the IEEE International Conference of Electron Devices and Solid-State Circuits, 2009, p. 221-224HfTiON gate dielectric is fabricated by reactive co-sputtering method followed by annealing in N 2 ambient. The effects of Ti content and annealing temperature on the performances of HfTiON gate-dielectric Si MOS devices are investigated. Experimental results indicate that gate capacitance is increased with increasing Ti content. However, when the Ti/Hf ratio exceeds -1.75, increase of the gate capacitance becomes small. Surface roughness of the samples annealed at different temperatures is analyzed by AFM, and results show that high annealing temperature (e.g. 700 °C for 30 s) can produce smooth surface, thus resulting in low gate leakage current. ©2009 IEEE.published_or_final_versio